Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation

Coarse-grained FPGA overlays built around the runtime programmable DSP blocks in modern FPGAs can achieve high throughput and improved scalability compared to traditional without detailed consideration of architecture. These be mapped using higher level compilers, achieving fast compilation, software-like programmability run-time management, high-level design abstraction. OpenCL allows programs running on a host computer launch accelerator kernels which compiled at for specific architecture, thus enabling portability. However, prohibitive hardware compilation times flows mean that tools cannot effectively use just-in-time (JIT) or performance scaling FPGAs. We present methodology dataflow graphs expressed as onto coarse-grained overlays. The benefits from abstraction afforded by programming model, while mapping overlay significantly reduces load times. Key characteristics this work include highly performant DSP-optimized functional units scale large devices ability perform automatic resource-aware kernel replication up size overlay. demonstrate place route orders magnitude better than HLS flows, even when an embedded processor Xilinx Zynq.